Semiconductor, Wafer Fabricator, Solar Expert Consultant Resume
Resume of NLF Lead Consultant

  • Semiconductor
  • Solar
  • Power
  • Consumer Electronics
  • Computers
  • Microchip

The expert was a President’s Fellow at The Georgia Institute of Technology and received a M.S.E.E.

This expert graduated Magna cum Laude and Phi Beta Kappa, from University of South Carolina with a B.S.E.

Semiconductor, Wafer Fabricator, Solar Expert Consultant Resume

This expert has worked in the electronics industry providing engineering consulting services and broad technical knowledge in electronic and semiconductor products and processes.

This consultant has provided expert witness services and testimony and has provided opinions and analyses to financial and investment analysts in the semiconductor and electronics sectors.

Also an experienced and successful builder and leader of R&D, engineering and manufacturing organizations, this consultant provides organizational and operational analysis and consulting services.

Experience ranges from a Naval Electronics Technician to Director of Engineering in a world-class wafer fab to CEO of chip startup companies. This expert has participated in the startups of nine wafer fabs. The associate is experienced in multi-national technology exchanges with Japanese, Korean, UK, and Israeli operations. The expert has further consulting experience with operations throughout North America, Europe, and Eastern Asia.

Consulting service areas include solar cell manufacturing, silicon cell processing, multi-junction cell processing, and array and collector and concentrator assemblies. Experienced with power supplies, power electronics, battery technology, and charging systems. Further areas are instrumentation and data acquisition including ultra-low-level and RF environments, semiconductor device and product engineering.

The expert’s background includes wafer probe, parametric test, laser repair and laser trim. Experience includes chip assembly and packaging, final test, and qualification. Additional specialization includes wafer fab process development, process architecture, and process optimization. More experience includes wafer fab design, layout, and tool selection. This associate is also familiar with yield enhancement, yield management, and process improvement, and defect reduction. Additionally, specialties are inspection plans, inspection tool selection, risk management, and data analysis with systematic problem analysis and resolution. This associate’s background includes cleanroom design, protocols, material selections, and contamination free manufacturing (CFM). Background includes model validation, silicon verification, and foundry selection and management. The expert also has worked with data acquisition selection, setup and optimization.

This expert has background with organizational analysis, staffing, and recruiting. including practices and procedures . Additionally, this person's background includes expert witness for product failure and liability as well as patent infringement including analyses, opinions and testimony. The expert has given advice to the investment communities on semiconductor and solar products, processes, and wafer fab and equipment issues.

Lead Consultant, Kevin Kennedy Associates Inc.

Providing product engineering consulting, semiconductor engineering consulting, product technology management, process architecture, device engineering, test engineering, wafer fabricator consulting, solar, power, and related expertise to a wide variety of clients.


President, CMOS technology firm

Led a multinational startup venture to commercialize the industry's first practical method of implementing multiple-valued logic functionality in standard CMOS process and design systems.


President, Sabal Semiconductor, Inc., Austin, TX

Formed and led a new startup venture to produce an innovative highly-integrated power supply design for the implementation and control of high-brightness LED's. This product enabled the use of LED's for the direct replacement of standard incandescent and halogen bulbs in commercial, industrial and household implementations. We produced the initial product design and working prototypes.


Consultant, Austin, TX

Provided consulting services on yield problems, device and process design, chip production economics, DRAM and module resale, wafer fab data analysis, and parametric test equipment design. Also provided consulting services to the legal and investment community.


Consulting Services Manager, Applied Materials, Austin, TX

Joined Applied through the acquisition of GKS. Was responsible for the delivery of consulting services for the Yield Enhancement Services group, proprietary data mining and analysis software used to identify and resolve yield, control and quality problems relating to products produced in the customers’ wafer fabs.


Consulting Services Director, Global Knowledge Services, Austin, TX

One of the founding partners of a new startup selling technology consulting services to wafer fab customers, hired and managed the consulting staff and developed the service offerings, supported tool development, account management, customer relations, and sales support, performed analysis of customer data for yield improvement services. Fortune 500 customers ranged from contact-print discrete lines to 130nm copper CMOS technology. Company acquired by Applied Materials.


Director of Product Technology, Samsung Austin Semiconductor, Austin, TX

Responsible for Product Engineering, Process Architecture (integration), Device Engineering, Test Engineering, Test Maintenance and Test Manufacturing. Assisted in building all of these groups from scratch as an early management hiree. State-of-the-art 200mm DRAM wafer fab startup, initial process set up for a 350nm 64M DRAM process. Led organization through four generations of technology and to best-in-the-world yields and AQL’s on a 230nm 128M process. My division had primary responsibility for the technology transfer, process setup and product qualification including yield, performance, and quality metric ownership. Also served as Chairman of the Process Change Control Board that drove the setup of the initial spec systems and approved all initial specs, controlled all process changes, test changes, and any technical spec change and all experimentation. Served on the HR, Policy, Patent and Philanthropy committees.


Sr. Manager of Technology Development, Computer and Communications Group, National Semiconductor Corp., Arlington, TX

Built new development group created by a strategic change to a distributed development model. Staffed, organized and directed organization to support a two-fab facility with process technologies including BiCMOS and CMOS mixed-signal, along with CMOS logic with embedded SRAM, and NVM technologies to 0.5um with advanced device structures and multilevel interconnects, including Process Integration, Device Engineering, Circuit, Process and Device modeling, DFM, and Unit Process development activities. Also managed the transfer of technology into our fabs and out of our fabs to other National fabs.


Engineering Manager, Computer and Communication Group, National Semiconductor Corp., Arlington, TX

Responsible for engineering activities in a startup submicron class-1 production fab, including Device Engineering, parametric test, SPC, yield modeling, yield enhancement, and CFM. Delivered an ahead-of-schedule fab startup with full device, process and fab qualification on first runs as well as yield on the first lot, wafer and die tested.


Principal Device Scientist, RISC Microprocessor Design, Semiconductor Products Sector, Motorola, Austin, TX

SPICE modeling and device characterization, design rule optimization, and the integration of the process development and circuit design efforts in support of the development of advanced RISC-based microprocessor products. Led the design of the process development and modeling test chips. Also served as the Principal Device Engineer for the Power PC transfer and completed the generation of the initial SPICE model files used by Motorola, IBM, and Somerset.

Principal Staff Engineer, DRAM Technology Dept., Semiconductor Products Sector, MOS Memory Products Division, Motorola, Austin, TX

Responsible for the Device Engineering activities to support the transfer of Toshiba 1M and 4M DRAM technology into production in Motorola and joint venture wafer fabs. Analyzed wafers, product and data from all fabs and compared the performance of the fabs to ensure that the process was matched and that the product was consistent from all wafer fabs, including modeling, parametric test, failure-analysis, and process characterization. Also supported other Motorola product and development groups with modeling, and device test and characterization. Provided engineering support for fab startup and production problems at all facilities including qual fail issues, yield issues and process improvements.

Principal Device Engineer, Bipolar Technology Development, Advanced Micro Devices, San Antonio, TX

Process and Device modeling and simulation in support of the development of advanced Bipolar processes. Developed models for dual-poly-emitter Bipolar devices from process definition through SPICE model decks, resulting in circuit performance modeling to within 10% of the initial Silicon, and continued this function through the technology exchange joint venture with Sony Corporation who subsequently bought the venture.

Process Development Engineering Manager, Fab X, Advanced Micro Devices, Austin, TX

Head of the engineering department responsible for the Device Engineering, Process Integration and yield enhancement functions. Developed new process technologies including the 64K DRAM, nMOS SRAM and a triple-poly (1.0 um) 16K FSRAM.

My group created and brought into production the process to produce the second-source Intel 80186 and 80286 processor families with superior performance, costs and yields versus the Intel process. Accountable for wafer sort, laser, parametric test, and yields in a then state-of-the-art 5" MOS wafer fab.

Device Engineering Supervisor, Modeling Department, Mostek Process R&D, Carrollton, TX

Lead the group that was responsible for the characterization of process experiments in support of the development of 64K, 256K and 1Mbit DRAM process technologies.

I was one of the principal contributors to the development of the process test vehicles and directed the layout of those designs. Designed the process verification structures, the test structures for the verification of design rule limitations, and defect arrays. One of the primary authors of the Design Rule Manual and the principal author of the Layout Design Rules and the modeling decks. Directed efforts toward HCE testing and transistor and interconnect reliability screening for process R&D. Supported Process R&D with modeling using SUPREM, SEDAN, Minimos and other tools. Developed the circuit models for the 64K cell/bitline structures and improved Mostek's proprietary SPICE model equations.

Bipolar Product Engineering Manager, Semiconductor Division, Data General Corp., Sunnyvale, CA

Responsible for process integration, device engineering, parametric testing, and new product introduction for bipolar product lines of >150 products. Process technologies ranged from diode arrays to bit-slice microprocessors and PALs. We produced every chip in the Nova and Eclipse computers. Author of the Composite Schottky Design Rules used for PALs, PROMs and uP's as well as the ECL design rules for gate array projects. Designed the process development test vehicles and supported the process development efforts for all processes.

Product Engineer, Monolithic Memories, Inc., Sunnyvale, CA

Responsible for the 8M family of Bipolar PROM's, PAL's, and the introduction of a new line of interface chips. Also helped debug and fix several process problems in support of the startup of a new 4” wafer fab.

Semiconductor device and product engineer, expertise on device or transistor design, product and process development, yield enhancement and process improvement. Assist product development projects (chip industry), with model validation, silicon verification and foundry selection and management. Manage failure analysis, reliability testing, and final test and assembly programs. Ensure success of first-rev silicon, provide support for redesign success. Provide project planning and management, and full business plan development consulting for startup or critical projects. Consultant to wafer fabricators for yield enhancement, problem solving, and process and operational improvement. Expert witness testimony, and patent infringement litigation, including analyses, opinions and testimony. Investment advisors for semiconductor products, processes, and wafer fab and equipment issues, technologies, needs and trends.

Multi-national technology exchanges with Japanese, Korean, UK, and Israeli operations, with consulting experience with operations in the US, Mexico, Japan, China, Taiwan, Singapore, France, and Italy

Participated in nine wafer fab startups at every level from NCG to Director of Engineering

Product lines include DRAM, SRAM and NVM, Microprocessor, Mixed-signal, Analog, Discrete RF and Power

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Peter Habicht, Lead Consultant
Peter specializes in welding and metallurgical engineer with 40 years industry experience in commercial nuclear power plant construction.


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